1. Field of the Invention
The present invention relates generally to integrated circuits and more particularly to protection for integrated circuits from transient electrostatic discharge (ESD).
2. Description of the Related Art
Electrostatic discharge (ESD) may cause damage to semiconductor devices on an integrated circuit during handling of the integrated circuit chip package. Specifically, integrated circuits are susceptible to electrostatic discharge (ESD) events that can either degrade the performances of circuits or may destroy them. Prevention of such damage generally is provided by protection circuits incorporated into the chip of the integrated circuit. In general, such protection circuits include a switch which is capable of conducting relatively large currents during an ESD event. Decreasing the size of the ESD protection circuitry while maintaining its performance would be desirable to increase integration or increase margins of integrated circuits.
FIG. 1A shows a cross section of a MOSFET to address electrostatic discharge (ESD) events. FIG. 1B shows a top view of FIG. 1A. Referring to FIGS. 1A and 1B, the ESD protection device 100 comprises a substrate 102 with trench isolations 104. A plurality of gates 106 are formed on the substrate 102 with a source region 110 and a drain region 108 disposed on opposite sides of each of the plurality of gates 106. A source contact 112 and a drain contact 114 alternatively contact the source regions 110 and the drain regions 108 (see FIG. 1B). The MOSFET device needs a large area to address high ESD, which hinders shrinkage for ESD design.